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copyright ? cirrus logic, inc. 1999 (all rights reserved) preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. CS4299 preliminary product data sheet crystalclear? soundfusion? audio codec 97 features n ac 97 2.1 compatible n industry leading mixed signal technology n 20-bit stereo digital-to-analog converter and 18-bit ste- reo analog to digital converter with sample rate conversion n four analog line-level stereo inputs for connection from line in, cd, video, and aux n two analog line-level mono inputs for modem sub- system and internal pc beeper n mono microphone input switchable from two external sources n high quality pseudo differential cd input n dual stereo line-level outputs n extensive power management support n meets or exceeds microsofts ? pc 98 and pc 99 audio performance requirements n crystalclear 3d stereo enhancement n s/pdif digital audio output n sample rate converters description t he CS4299 is an ac 97 2.1 compatible stereo audio codec designed for pc multimedia systems. using the industry leading crystalclear delta-sigma and mixed signal technology, the CS4299 paves the way for pc 98 and pc 99-compliant desktop, portable, and entertainment pcs, where high-quality audio is required. the CS4299, when coupled with a pci audio ac- celerator or core logic supporting the ac 97 interface, implements a cost effective, superior quality, audio solution. the CS4299 surpasses au- dio quality standards such as pc 98, pc 99, and ac 97 2.1. ordering info CS4299 -kq, 48-pin tqfp, 9x9x1 mm CS4299 -jq, 48-pin tqfp, 9x9x1 mm ds319pp3 feb 99 ac'97 registers line cd aux video mic1 mic2 phone pc_beep line_out alt_line_out mono_out analog input mux and output mixer ac-link and ac'97 registers pcm_data gain / mute controls input mux s output mixer mixer / mux selects ac- link pwr mgt sync bit_clk sdata_out sdata_in reset# pcm_data dac 20 bits adc 18 bits src src s/pdif
2 ds319pp3 CS4299 crystalclear? soundfusion? audio codec 97 table of contents 1.0 characteristics and specifications ...........................................4 analog characteristics .................................................................................4 mixer characteristics....................................................................................5 absolute maximum ratings .........................................................................5 recommended operating conditions ..........................................................5 digital characteristics ..................................................................................5 serial port timing.........................................................................................6 2.0 general description ...........................................................................9 2.1 ac-link .................................................................................................9 2.2 control registers ...................................................................................9 2.3 sample rate converters ....................................................................10 2.4 output mixer .......................................................................................10 2.5 input mux ............................................................................................10 2.6 volume control ...................................................................................10 3.0 ac 97 frame definition ......................................................................12 3.1 ac-link serial data output frame .....................................................12 serial data output slot tags (slot 0) .................................................12 register address (slot 1) ....................................................................12 register write data (slot 2) ................................................................13 playback data (slots 3-10) .................................................................13 3.2 ac-link audio input frame ................................................................13 serial data input slot tag bits (slot 0) ..............................................13 read-back address port (slot 1) ........................................................14 read-back data port (slot 2) .............................................................14 pcm capture data (slot 3-10) ............................................................14 3.3 ac 97 reset modes ...........................................................................14 cold ac 97 reset ..............................................................................14 warm ac 97 reset ............................................................................14 ac 97 register reset ........................................................................15 3.4 ac-link protocol violation - loss of sync ........................................15 4.0 register interface ............................................................................16 reset (index 00h) ..............................................................................17 master volume (index 02h) ...............................................................17 alternate volume (index 04h) ............................................................17 master mono volume (index 06h) .....................................................18 pc_beep volume (index 0ah) .........................................................18 phone volume (index 0ch) ................................................................18 microphone volume (index 0eh) ........................................................18 stereo analog mixer input gain (indexs 10h - 18h) ...........................19 input mux select (index 1ah) .............................................................19 record gain (index 1ch) ....................................................................19 microsoft is a registered trademark of microsoft corporation in the united states and/or other countries. intel is a registered trademark of intel corporation. crystal clear and sound fusion are trademarks of cirrus logic. cirrus logic, inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. h owever, the infor- mation is subject to change without notice and is provided as is without warranty of any kind (express or implied). no respon sibility is assumed by cirrus logic, inc. for the use of this information, nor for infringements of patents or other rights of third parties. this document is the property of cirrus logic, inc. and implies no license under patents, copyrights, trademarks, or trade secrets. no part of this publicati on may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise). fur- thermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written con sent of cirrus logic, inc. the names of products of cirrus logic, inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. a list of cirrus logic, inc. trademarks and service m arks can be found at http://www.cirrus.com.
ds319pp3 3 CS4299 crystalclear? soundfusion? audio codec 97 general purpose (index 20h) ............................................................. 20 3d control (index 22h) ....................................................................... 20 powerdown control/status (index 26h) .............................................. 21 extended audio id (index 28h) .......................................................... 21 extended audio status / control (index 2ah) .....................................22 pcm front dac rate (index 2ch) ..................................................22 pcm lr adc rate (index 32h) .......................................................... 22 slot map (index 5eh) .......................................................................... 23 s/pdif control (index 68h) ................................................................ 24 vendor id1 (index 7ch) .....................................................................24 vendor id2 (index 7eh) ...................................................................... 25 5.0 power management ........................................................................... 26 6.0 analog hardware description .................................................... 26 6.1 line-level inputs ................................................................................ 26 6.2 microphone level inputs .................................................................... 27 6.3 mono inputs ........................................................................................ 27 6.4 line level outputs ............................................................................. 28 6.5 miscellaneous analog signals ............................................................ 29 6.6 consumer iec-958 digital interface (s/pdif) .................................... 29 6.7 power supplies ..................................................................................30 7.0 grounding and layout .....................................................................30 8.0 pin descriptions ..................................................................................32 digital i/o pins .................................................................................... 32 analog i/o pins ..................................................................................34 filter and reference pins ................................................................... 36 power supplies ..................................................................................36 9.0 parameter and term definitions ................................................. 38 10.0 references ........................................................................................... 40 11.0 package dimensions .......................................................................... 41
4 ds319pp3 CS4299 crystalclear? soundfusion? audio codec 97 1.0 characteristics and specifications analog characteristics (standard test conditions unless otherwise noted: t ambient = 25 c, avdd = 5.0 v 5%, dvdd = 3.3 v 5%; 1 khz input sine wave; sample frequency, fs = 48 khz; z al =10 k w/ 680 pf load, c dl = 18 pf load (note 1); measurement bandwidth is 20 hz - 20 khz, 18-bit linear coding for adc functions, 20-bit linear coding for dac functions; mixer registers set for unity gain. notes: 1. z al refers to the analog output pin loading and c dl refers to the digital output pin loading. 2. parameter definitions are given in the parameter and term definitions section. 3. path refers to the signal path used to generate this data. these paths are defined in the parameter and term definitions section. 4. this specification is guaranteed by silicon characterization, it is not production tested. parameter (note 2) symbol path (note 3) CS4299-kq CS4299-jq unit min typ max min typ max full scale input voltage line inputs mic inputs (20db = 0) mic inputs (20db = 1) a-d a-d a-d 0.91 0.91 0.091 1.00 1.00 0.10 - - - 0.91 0.91 0.091 1.00 1.00 0.10 - - - v rms v rms v rms full scale output voltage line,alternate line, and mono outputs d-a 0.91 1.0 1.13 0.91 1.0 1.13 v rms frequency response (note 4) analog ac = 0.5 db dac ac = 0.5 db adc ac = 0.5 db fr a-a d-a a-d 20 20 20 - - - 20,000 20,000 20,000 20 20 20 - - - 20,000 20,000 20,000 hz hz hz dynamic range stereo analog inputs to line_out mono analog inputs to line_out dac dynamic range adc dynamic range dr a-a a-a d-a a-d 90 85 85 85 95 90 90 90 - - - - - - - - 90 85 87 85 - - - - db fs a db fs a db fs a db fs a dac snr (-20 db fs input w/ ccir-rms filter on output) snr d-a - 70 - - - - db total harmonic distortion + noise (-3 db fs input signal): line/alternate line output dac adc (all inputs except phone/mic) adc (phone/mic) thd+n a-a d-a a-d a-d - - - - -90 -87 -84 -85 -80 -80 -80 -74 - - - - - - - - -74 -74 -74 -74 db fs db fs db fs db fs power supply rejection ratio (1 khz, 0.5 v rms w/ 5 v dc offset)(note 4) 40 60 - - 40 - db interchannel isolation 70 87 - - 87 - db spurious tone (note 4) - -100 - - -100 - db fs input impedance (note 4) 10 - - 10 - - k w external load impedance 10 - - 10 - - k w output impedance (note 4) - 730 - - 730 - w input capacitance (note 4) - 5 - - 5 - pf vrefout 2.0 2.3 2.5 2.0 2.3 2.5 v
ds319pp3 5 CS4299 crystalclear? soundfusion? audio codec 97 mixer characteristics (for CS4299 -kq only) absolute maximum ratings (avss1 = avss2 = dvss1 = dvss2 = 0 v) recommended operating conditions (avss1 = avss2 = dvss1 = dvss2 = 0 v) digital characteristics (avss = dvss = 0 v (see grounding and layout section)) parameter min typ max unit mixer gain range span line in, aux, cd, video, mic1 mic2, phone, pc beep, alternate line mono out line out - - - 46.5 46.5 94.5 - - - db db db step size all volume controls except pc beep pc beep - - 1.5 3.0 - - db db parameter min typ max unit power supplies +3.3 v digital +5 v digital analog -0.3 -0.3 -0.3 - - - 6.0 6.0 6.0 v v v total power dissipation (supplies, inputs, outputs) - - tbd mw input current per pin (except supply pins) -10 - 10 ma output current per pin (except supply pins) -15 - 15 ma analog input voltage -0.3 - avdd+ 0.3 v digital input voltage -0.3 - dvdd + 0.3 v ambient temperature (power applied) -55 - 110 c storage temperature -65 - 150 c parameter symbol min typ max unit power supplies +3.3 v digital +5 v digital analog dvdd1, dvdd2 dvdd1, dvdd2 avdd1, avdd2 3.135 4.75 4.75 3.3 5 5 3.465 5.25 5.25 v v v operating ambient temperature 0 - 70 c parameter symbol min typ max unit low level input voltage v il - -0.35 x dvddv high level input voltage v ih 0.65 x dvdd - - v high level output voltage v oh 0.90 x dvdd 0.99 x dvdd - v low level output voltage v ol - 0.03 0.10 x dvdd v input leakage current (ac-link inputs) -10 - 10 a output leakage current (tri-stated ac-link outputs) -10 - 10 a output buffer drive current (note 4) - tbd a
6 ds319pp3 CS4299 crystalclear? soundfusion? audio codec 97 serial port timing standard test conditions unless otherwise noted: t ambient = 25 c, avdd = 5.0 v, dvdd = 3.3 v; c l = 55 pf load. parameter symbol min typ max unit reset timing reset# active low pulse width t rst_low 1.0 - - m s reset# inactive to bit_clk start-up delay t rst2clk -tbd-ms 1st sync active to codec ready set t sync2crd - 41.6 - m s vdd stable to reset inactive t vdd2rst# tbd clocks bit_clk frequency f clk - 12.288 - mhz bit_clk period t clk_period - 81.4 - ns bit_clk output jitter (depends on xtal_in source) - - 750 ps bit_clk high pulse width t clk_high 36 40.7 45 ns bit_clk low pulse width t clk_low 36 40.7 45 ns sync frequency f sync -48-khz sync period t sync_period - 20.8 - m s sync high pulse width t sync_high -1.3- m s sync low pulse width t sync_low - 19.5 - m s data setup and hold output propagation delay from rising edge of bit_clk t prop -68ns output hold from falling edge of bit_clk t ohold 5- -ns input setup time from falling edge of bit_clk t isetup 10 - - ns input hold time from falling edge of bit_clk t ihold 0- -ns input signal rise time t irise 2-6ns input signal fall time t ifall 2-6ns output signal rise time (note 4) t orise 246ns output signal fall time (note 4) t ofall 246ns misc. timing parameters end of slot 2 to bit_clk, sdata_in low (pr4) t s2_pdown -.341.0 m s sync pulse width (pr4) warm reset t sync_pr4 1.0 - - m s sync inactive (pr4) to bit_clk start-up delay t sync2clk 162.8 244 - ns setup to trailing edge of reset# (ate test mode) (note 4) t setup2rst 15 - - ns rising edge of reset# to hi-z delay (note 4) t off - - 25 ns
ds319pp3 7 CS4299 crystalclear? soundfusion? audio codec 97 bit_clk t rst_low t rst2clk t vdd2rst# vdd reset# power up timing clocks bit_clk sync t irise t ifall t orise t ifall t clk_high t clk_low t sync_high t sync_low t sync_period t clk_period codec ready from startup or fault condition bit_clk t sync2crd codec_ready sync
8 ds319pp3 CS4299 crystalclear? soundfusion? audio codec 97 bit_clk t isetup t ohold t ihold sdata_out, sync sdata_in t prop bit_clk t s2_pdown sdata_in sdata_out sync write to 0x20 data pr4 don't care slot 1 slot 2 sync_pr4 sync2clk t t reset# sdata_out, sync t setup2rst sdata_in, t off bit_clk hi-z data setup and hold pr4 powerdown and warm reset test mode
ds319pp3 9 CS4299 crystalclear? soundfusion? audio codec 97 2.0 general description the CS4299 is a mixed-signal serial codec compliant to the audio codec 97 specification , revision 2.1 [1]. it is designed to be paired with a digital interface, referred to as the controller, which is typ- ically located on the pci bus or integrated within the system chip set. the controller is responsible for all communications between the CS4299 and the remainder of the system. the codec contains two distinct functional sections: digital and analog. the digital section includes the ac-link regis- ters, sample rate converters, power management support, and ac-link serial port interface logic. the analog section includes the analog input multiplexer (mux), stereo output mixer, mono output mixer, stereo adcs, stereo dacs, and their associated volume controls. 2.1 ac-link all communication with the codec is estab- lished with a 5-wire digital interface to the con- troller chip as shown in figure 1. all clocking for the serial communication is synchronous to the bit_clk signal. bit_clk is generated by the primary codec and is used to slave the con- troller and any secondary codecs, if applicable. an ac-link audio frame is a sequence of 256 se- rial bits organized into 13 groups referred to as slots. one frame consists of one 16-bit slot and twelve 20-bit slots. during each audio frame, data is passed bi-directionally between the co- dec and the controller. the input frame is driv- en from the codec on the sdata_in line. the output frame is driven from the controller sdata_out line. both input and output frames contain the same number of bits and are organized with the same slot configuration. the input and output frame have differing functions for each slot. the controller synchronizes the beginning of a frame with the sync signal. in figure 2 the position of each bit location within the frame is noted. the first bit position in a new serial data frame is f0 and the last bit position in the serial data frame is f255. when sync goes active (high) and is sampled active by the CS4299 (on the falling edge of bit_clk), both devices are synchronized to a new serial data frame. the data on the sdata_out pin at this clock edge is the final bit of the previous frames serial data. on the next rising edge of bit_clk, the first bit of slot 0 is driven by the controller on the sdata_out pin. the CS4299 latches in this data, as the first bit of the frame, on the next falling edge of the bit_clk clock signal. the controller is also responsible for issuing reset via the reset# signal. after being reset, the co- dec is responsible for flagging the controller that it is ready for operation after synchronizing its in- ternal functions. the ac-link signals may be referenced to either 5 volts or 3.3 volts. the CS4299 must use the same digital supply voltage as the controller chip. 2.2 control registers all read accesses to the codec are generated by requesting a register address (index number) in slot 1 of a sdata_out frame. the following sdata_in frame will contain the register content in its codec sync bit_clk sdata_out sdata_in reset# digital ac'97 controller figure 1. ac-link connections
10 ds319pp3 CS4299 crystalclear? soundfusion? audio codec 97 slot 2. the write operation is identical with the index in slot 1 and the write data in slot 2. the ac 97 frame definition section details the function of each input and output frame. individual register de- scriptions are found in the register interface section. 2.3 sample rate converters the sample rate converters (src) provide high accuracy digital filters supporting sample frequen- cies other than 48 khz to be played or captured from the codec. in addition to the 48 khz rate, the CS4299 supports the windows standard sample rates of 8.0 khz, 11.025 khz, 16 khz, 22.05 khz, 32 khz, and 44.1 khz. 2.4 output mixer there are two output mixers on the CS4299 as illustrated in figure 3. the stereo output mixer sums together the analog inputs to the CS4299 according to the settings in the volume control registers. the mono output mixer generates a monophonic sum of the left and right channels from the stereo input mixer. however, the mono output mixer does not include the pc_beep and phone signals which are included in the stereo output mix. the stereo output mix is sent to the line_out and alt_line_out output pins of the CS4299. the mono output mix is sent to the mono_out out- put pin on the CS4299. 2.5 input mux the input multiplexer controls which analog input is sent to the adcs. the output of the input mux is converted to stereo 18-bit digital pcm data and sent to the controller chip via the ac-link sdata_in signal. 2.6 volume control the codecs volume control registers control analog input level to the input mixer, the master vol- ume level, and the alternate volume level. all analog volume controls, except pc_beep, implement controlled volume steps at nominally 1.5 db per step. pc_beep uses 3 db steps. the analog inputs 20.8 m s (48 khz) tag phase data phase 12.288 mhz 81.4 ns sync bit_clk sdata_out sdata_in f0 f1 f2 f16 f15 f14 f13 f12 f35 f56 f76 0 f255 valid frame slot 1 valid 00 scra1 scra0 r/w 0 wd15 f36 f57 lp19 lp18 rp19 lc17 lc16 rc17 rd15 0 0 0 0 0 bit frame position: f0 f1 f2 f16 f15 f14 f13 f12 f35 f56 f76 f255 f36 f57 f255 f255 x x 0 0 f97 f97 x slot 0 slot 1 slot 2 slot 3 slot 4 slots 5-12 slot 2 valid slot 1 valid slot 2 valid codec ready 0 bit frame position: figure 2. ac-link input and output framing
ds319pp3 11 CS4299 crystalclear? soundfusion? audio codec 97 allow a mixing range of +12 db of signal gain to -34.5 db of signal attenuation. the analog output volume controls allow from 0 db to -94.5 db of attenuation for line_out and -46.5 db for alt_line_out and mono_out. the pc_beep input volume control allows from 0 db to -45 db of attenuation. v o l mic1 mic2 line cd video aux alt line out line_out ac-link interface 2 2 2 2 2 sdata_out reset# sync sdata_in bit_clk codec id 2 +20db mute mute mute mute mute mute mute dac s s v o l v o l v o l v o l v o l phone v o l v o l mut e pc beep v o l s 1/2 v o l s 1/2 v o l mono out loopback mode s/pdif out mute mute mute v o l v o l output mixer 6-bit volume control 5-bit volume control 5-bit volume control mute adc 3d processing dac direct mode (ddm) 1 0 b u f stereo to mono mixer stereo to mono mixer mono select analog stereo input mixer adc input mux main a/d gain main d/a converters mic select pcm out master volume alternate volume mono volume figure 3. mixer diagram
12 ds319pp3 CS4299 crystalclear? soundfusion? audio codec 97 3.0 ac 97 frame definition the ac link is a bi-directional serial port with thirteen time-division multiplexed slots in each di- rection. the first slot is 16 bits long and termed the tag slot. bits in the tag slot determine if the codec is ready and indicate which, if any, other slots contain valid data. slots 1 through 12 are 20-bits long and can contain audio data. slot 11 and slot 12 are not utilized on the CS4299. the serial data line is defined from the controllers perspective, not from the audio codecs perspective. 3.1 ac-link serial data output frame in the serial data output frame, data is passed on the sdata_out pin to the CS4299 from the controller. figure 2 illustrates the serial port timing. serial data output slot tags (slot 0) valid frame determines if any of the following slots contain either valid playback data for the codecs dacs or data for read/write operation. when set, at least one of the other ac-link slots contain valid data. if this bit is clear, the remainder of the frame is ignored. slot [1:2] valid indicates valid slot data when accessing the register set of the primary codec (scra[1:0] = 00). for a read operation, slot 1 valid is set when register address (slot 1) contains valid data. for a write operation, slot 1 valid and slot 2 valid are set indicating register address (slot 1) and reg- ister write data (slot 2) contain valid data. the register address and write data must be valid within the same frame. scra[1:0] must be cleared when accessing the primary codec. the physical ad- dress of a codec is determined by the id[1:0]# input pins which are reflected in the extended audio id (index 28h) register. slot [3:10] valid if a slot valid bit is set, the named slot contains valid audio data. if the bit is clear, the slot will be ignored. the codec supports alternate slot mapping as defined in the ac 97 2.1 specification [1]. for more information, see the slot map (index 5eh) register. scra[1:0] secondary codec register access. unlike the primary codec, scra[1:0] indicate valid slot data when accessing the register set of a secondary codec. the value set in scra[1:0] (01,10,11) de- termines which of the three possible secondary codecs is accessed. for a read operation, the scra[1:0] bits are set when register address (slot 1) contains valid data. for a write operation, scra[1:0] bits are set when register address (slot 1) and register write data (slot 2) contain valid data. the write operation requires the register address and the write data to be valid within the same frame. scra[1:0] must be cleared when accessing the primary codec. they must also be cleared during the idle period where no register read or write is pending. the physical address of a codec is determined by the id[1:0]# input pins which are reflected in the extended audio id (index 28h) register. the scra[1:0] bits are listed as the id[1:0] bits in slot 0 in the ac 97 specification. register address (slot 1) r/w read/write . determines if a read (r/w = 1) or write (r/w = 0) operation is requested. for a read operation, the following input frame will return the register index in the read-back address port (slot 1) and the contents of the register in the read-back data port (slot 2). a write operation does not return any valid data in the following frame. if the r/w bit = 0, data must be valid in both the register address (slot 1) and the register write data (slot 2) during a frame when slot [1:2] valid or scra[1:0] are set. bit 1514131211109876543210 valid frame slot 1 valid slot 2 valid slot 3 valid slot 4 valid slot 5 valid slot 6 valid slot 7 valid slot 8 valid slot 9 valid slot 10 valid scra 1 scra 0 bit 191817161514131211109876543210 r/w ri6 ri5 ri4 ri3 ri2 ri1 ri0
ds319pp3 13 CS4299 crystalclear? soundfusion? audio codec 97 ri[6:0] register index/address. registers can only be accessed on word boundaries; ri0 must be set to 0. ri[6:0] must contain valid data during a frame when the slot 1 valid or scra[1:0] are set. register write data (slot 2) wd[15:0] codec register data for write operations. for read operations, this data is ignored. if r/w = 0, data must be valid in both the register address (slot 1) and the register write data (slot 2) during a frame when the slot [1:2] valid = 11 or either scra[1:0] bit is set. splitting the register address and the write data across multiple frames is not permitted. playback data (slots 3-10) pd[19:0] 20-bit pcm playback (2s compliment) data for the left and right dacs and/or the s/pdif transmit- ter. any pcm data from the controller less than 20 bits should be left justified in the slot and ze- ro-padded. table 8 on page 24 lists the definition of each respective slot. the mapping of a given slot to a dac is determined by the state of the id[1:0] bits found in the extended audio id (index 28h) register and by the sm[1:0] and amap bits found in the slot map (index 5eh) register . 3.2 ac-link audio input frame in the serial data input frame, data is passed on the sdata_in pin from the CS4299 to the ac 97 controller. the data format for the input frame is very similar to the output frame. figure 2 illustrates the serial port timing. serial data input slot tag bits (slot 0) codec ready indicates the readiness of the CS4299 s ac-link and control and status registers. immediately after a cold reset this bit will be clear. once the CS4299s clocks and voltages are stable, this bit will be set. until the codec ready bit is set, no ac-link transactions should be attempted by the controller. the codec ready bit does not indicate readiness of the dacs, adcs, vref, or any other analog function. those must be checked in the powerdown control/status (index 26h) register by the con- troller before any access is made to the mixer registers. any accesses to the codec while codec ready is clear is ignored. slot 1 valid tag indicates slot 1 contains a valid read back address. slot 2 valid tag indicates slot 2 contains valid register read data. slot [3:10] valid tag indicates slot [3:10] contains valid capture data from the codecs adc. bit 19181716151413121110987654 3210 wd15 wd14 wd13 wd12 wd11 wd10 wd9 wd8 wd7 wd6 wd5 wd4 wd3 wd2 wd1 wd0 bit 191817161514131211109876543210 pd19 pd18 pd17 pd16 pd15 pd14 pd13 pd12 pd11 pd10 pd9 pd8 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 bit 1514131211109876543210 codec ready slot 1 valid slot 2 valid slot 3 valid slot 4 valid slot 5 valid slot 6 valid slot 7 valid slot 8 valid slot 9 valid slot 10 valid
14 ds319pp3 CS4299 crystalclear? soundfusion? audio codec 97 read-back address port (slot 1) ri[6:0] register index. the read-back address port echoes the ac 97 register address when a register read has been requested in the previous frame. the codec will only echo the register index for a read access. write accesses will not return valid data in slot 1. drs[3:10] disable request for slots 3 - 10. when the vre bit in extended audio status / control (index 2ah) register is clear, these bits are always 0. when vre is set, the srcs are enabled and the codec will set these bits when the srcs do not need data. when the controller sees these bits set, it must not send data on sdata_out in the following frame (not the current frame). read-back data port (slot 2) rd[15:0] 16-bit register value. the read-back data port contains the register data requested by the control- ler from the previous read request. all read requests will return the read address in the read-back address port (slot 1) and the register data in the read-back data port (slot 2) on the following se- rial data frame. pcm capture data (slot 3-10) cd[17:0] 18-bit pcm (2s compliment) data. the mapping of a given slot to an adc is determined by the state of the id[1:0] bits found in the extended audio id (index 28h) register and the sm[1:0] and amap bits found in the slot map (index 5eh) register . the definition of each slot can be found in table 7 on page 23. the capture data in slot [3:10] will only be valid when the respective slot valid bit is set in slot 0. 3.3 ac 97 reset modes three methods of resetting the CS4299 , as defined in the ac 97 specification, are supported: cold ac 97 reset , warm ac 97 reset , and ac 97 register reset . a cold ac 97 reset is required to restart the ac-link when bit pr5 is set in the powerdown control/status (index 26h) register. cold ac 97 reset a cold reset is performed by asserting reset# in accordance with the minimum timing specifica- tions in the serial port timing section. once de-asserted, all of the codecs registers will be reset to their default power-on states and the bit_clk clock and sdata_in signals will be reactivated. the timing of power-up/reset events is discussed in detail in the power management section. warm ac 97 reset the CS4299 may also be reactivated when the ac-link is powered down (refer to the pr4 bit de- scription in the power management section) by a warm reset. a warm reset allows the ac-link to be reactivated without losing information in the codecs registers. warm reset is initiated when the sync signal is driven high for at least 1 s and then driven low in the absence of the bit_clk clock signal. the bit_clk clock will not restart until at least 2 normal bit_clk clock periods ( 162.8 ns) after the sync signal is de-asserted. bit 19181716151413121110987 65 4 3210 ri6 ri5 ri4 ri3 ri2 ri1 ri0 drs3 drs4 drs5 drs6 drs7 drs8 drs9 drs10 bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rd15 rd14 rd13 rd12 rd11 rd10 rd9 rd8 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 bit 191817161514131211109876543210 cd17 cd16 cd15 cd14 cd13 cd12 cd11 cd10 cd9 cd8 cd7 cd6 cd5 cd4 cd3 cd2 cd1 cd0
ds319pp3 15 CS4299 crystalclear? soundfusion? audio codec 97 ac 97 register reset the third reset mode provides a register reset to the CS4299. this is available only when the CS4299 s ac-link is active and the codec ready bit is set. the register reset forces all registers to be reset to their default, power-up values. a register reset occurs when any value is written to the reset (index 00h) register. 3.4 ac-link protocol violation - loss of sync the CS4299 is designed to handle sync protocol violations. the following are situations where the sync protocol has been violated: ? the sync signal is not sampled high for exactly 16 bit_clk clock cycles at the start of an audio frame. ? the sync signal is not sampled high on the 256th bit_clk clock period after the previous sync assertion. ? the sync signal goes active high before the 256th bit_clk clock period after the previous sync assertion. upon loss of synchronization with the controller, the codec will mute all analog outputs and clear the codec ready bit in the serial data input frame until two valid frames are detected. during this detection period, the codec will ignore all register reads and writes and will discontinue the trans- mission of pcm capture data.
16 ds319pp3 CS4299 crystalclear? soundfusion? audio codec 97 4.0 register interface reg num name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 00h reset se4 se3 se2 se1 se0 0 id8 id7 0 0 id4 0 0 0 0 1990h 02h master volume mute ml5 ml4 ml3 ml2 ml1 ml0 mr5 mr4 mr3 mr2 mr1 mr0 8000h 04h alternate line out volume mute ml4 ml3 ml2 ml1 ml0 mr4 mr3 mr2 mr1 mr0 8000h 06h master volume mono mute mm4 mm3 mm2 mm1 mm0 8000h 0ah pc_beep volume mute pv3 pv2 pv1 pv0 0000h 0ch phone volume mute gn4 gn3 gn2 gn1 gn0 8008h 0eh mic volume mute 20db gn4 gn3 gn2 gn1 gn0 8008h 10h line in volume mute gl4 gl3 gl2 gl1 gl0 gr4 gr3 gr2 gr1 gr0 8808h 12h cd volume mute gl4 gl3 gl2 gl1 gl0 gr4 gr3 gr2 gr1 gr0 8808h 14h video volume mute gl4 gl3 gl2 gl1 gl0 gr4 gr3 gr2 gr1 gr0 8808h 16h aux volume mute gl4 gl3 gl2 gl1 gl0 gr4 gr3 gr2 gr1 gr0 8808h 18h pcm out vol mute gl4 gl3 gl2 gl1 gl0 gr4 gr3 gr2 gr1 gr0 8808h 1ah record select sl2 sl1 sl0 sr2 sr1 sr0 0000h 1ch record gain mute gl3 gl2 gl1 gl0 gr3 gr2 gr1 gr0 8000h 20h general purpose 3d mix ms lpbk 0000h 22h 3d control s3 s2 s1 s0 0000h 26h powerdown ctrl/stat eap d pr6 pr5 pr4 pr3 pr2 pr1 pr0 ref anl dac adc 000fh 28h extended audio id id1 id0 am ap vra 0201h 2ah extended audio ctrl vre 0000h 2ch pcm front dac rate sr 15 sr 14 sr 13 sr 12 sr 11 sr 10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 bb80h 32h pcm left/right adc rate sr 15 sr 14 sr 13 sr 12 sr 11 sr 10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 bb80h cirrus defined registers : 5e slot map register dd m ame n sm1 sm0 0080h 68 s/pdif enable spe n v fs l cc6 cc5 cc4 cc3 cc2 cc1 cc0 pre cop y #au dio pro 0000h 7ch vendor id1(cr) f7 f6 f5 f4 f3 f4 f1 f0 s7 s6 s5 s4 s3 s2 s1 s0 4352h 7eh vendor id2(y-) t7 t6 t5 t4 t3 t2 t1 t0 pid2 pid1 pid0 rid2 rid1 rid0 5931h table 1. mixer registers
ds319pp3 17 CS4299 crystalclear? soundfusion? audio codec 97 reset (index 00h) se[4:0] 3d stereo enhancement technique. 00110 - crystal 3d stereo enhancement. id8 set 18-bit adc resolution. id7 set 20-bit dac resolution. id4 set headphone out support. (alternate line output) read-only data 1990h any write to this register causes a register reset of the codecs registers forcing all registers to their default state. reads return configuration information about the codec. master volume (index 02h) mute master mute for the line_out_l and the line_out_r output signals. ml[5:0] master volume control for line_out_l pin. least significant bit represents -1.5 db with 00000 = 0 db. the total range is 0 db to -94.5 db. mr[5:0] master volume control for line_out_r pin. least significant bit represents -1.5 db with 00000 = 0 db. the total range is 0 db to -94.5 db. default 8000h, corresponding to 0 db attenuation and mute on. alternate volume (index 04h) mute master mute for the alt_line_out_l and the alt_line_out_r output signals. ml[4:0] master volume control for alt_line_out_l pin. least significant bit represents -1.5 db with 00000 = 0 db. the total range is 0 db to -46.5 db. ml5 setting ml5 sets the left channel attenuation to -46.5 db by forcing ml[4:0] to a 1 state. ml[5:0] will read back 01111 when ml5 has been set. see table 2. mr[4:0] master volume control for alt_line_out_r pin. least significant bit represents -1.5 db with 00000 = 0 db. the total range is 0 db to -46.5 db. mr5 setting mr5 sets the right channel attenuation to -46.5 db by forcing mr[4:0] to a 1 state. mr[5:0] will read back 011111 when mr5 has been set. see table 2. default 8000h, corresponding to 0 db attenuation and mute on. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 se4se3se2se1se00id8id700id40000 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute ml5 ml4 ml3 ml2 ml1 ml0 mr5 mr4 mr3 mr2 mr1 mr0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute ml5 ml4 ml3 ml2 ml1 ml0 mr5 mr4 mr3 mr2 mr1 mr0 ml[5:0]/mr[5:0]/mm[5:0] write ml[5:0]/mr[5:0]/mm[5:0 read gain level 000000 000000 0 db 000001 000001 -1.5 db ... 011111 011111 -46.5 db ... ... ... 1xxxxx 011111 -46.5 db table 2. alternate line-out and master mono attenuation
18 ds319pp3 CS4299 crystalclear? soundfusion? audio codec 97 master mono volume (index 06h) mute when set, mutes the mono_out signal. mm[4:0] master mono attenuation. least significant bit represents -1.5 db with 00000 = 0 db. the total range is 0 db to -46.5 db. mm5 setting mm5 sets the master mono attenuation to -46.5 db by forcing mm[4:0] to a 1 state. mm[5:0] will read back 011111 when mm5 has been set. see table 2. default 8000h, corresponding to 0 db attenuation and mute set. pc_beep volume (index 0ah) mute when set, mutes the pc_beep signal. pv[3:0] volume control for pc_beep pin. least significant bit represents -3 db with 0000 = 0 db. the total range is 0 db to -45 db. default 0000h, unmuted, with 0 db attenuation after the CS4299 is removed from the reset state. phone volume (index 0ch) mute when set mutes the phone signal. gn[4:0] phone volume control. least significant bit represents 1.5 db with 01000 = 0 db. the total range is 12 db to -34.5 db. default 8008h, 0 db attenuation and mute set. microphone volume (index 0eh) mute when set, mutes mic1/mic2 signal. gn[4:0] mic1/mic2 volume control. least significant bit represents 1.5 db with 01000 = 0 db. the total range is 12 db to -34.5 db. 20db enables 20 db microphone gain block. default 8008h, 0 db attenuation and mute set. this register controls the gain level of the microphone input source to the input mixer. it also con- trols the +20 db gain block which connects to the input volume control and to the input record mux. the selection of mic1 or mic2 input pins is controlled by the ms bit in the general purpose (index 20h) register. the gain mapping for this register is shown in table 3. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute mm5 mm4 mm3 mm2 mm1 mm0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute pv3 pv2 pv1 pv0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute gn4 gn3 gn2 gn1 gn0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute 20db gn4 gn3 gn2 gn1 gn0 gn4 - gn0 gain level mic gain with 20db = 1 00000 +12.0 db +32.0 db 00001 +10.5 db 30.5 db ... 00111 +1.5 db 21.5 db 01000 0.0 db 20.0 db 01001 -1.5 db 18.5 db ... 11111 -34.5 db -14.5 db table 3. analog mixer input gain values
ds319pp3 19 CS4299 crystalclear? soundfusion? audio codec 97 stereo analog mixer input gain (indexs 10h - 18h) mute when set mutes the respective input. setting this bit mutes both right and left inputs. gl[4:0] left volume control. least significant bit represents 1.5 db with 01000 = 0 db. the total range is 12 db to -34.5 db. see table 3. gr[4:0] right volume control. least significant bit represents 1.5 db with 01000 = 0 db. the total range is 12 db to -34.5 db. see table 3. default 8808h, 0 db gain with mute enabled. these registers control the gain levels of the analog input sources to the input mixer. the analog in- puts associated with registers 10h-18h are found in table 4. input mux select (index 1ah) sl[2:0] left channel adc input source select. sr[2:0] right channel adc input source select. default 0000h, mic inputs selected for both channels. when capturing pcm data, this register controls the input mux for the adcs. table 5 below lists the possible values for each input. record gain (index 1ch) mute when set, mutes the input to the adcs. gl[3:0] left adc gain. least significant bit represents +1.5 db with 0000 = 0 db. the total range is 0 db to +22.5 db. gr[3:0] right adc gain. least significant bit represents +1.5 db with 0000 = 0 db. the total range is 0 db to +22.5 db. default 8000h, 0 db gain with mute on. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute gl4 gl3 gl2 gl1 gl0 gr4 gr3 gr2 gr1 gr0 register index function 10h line in volume 12h cd volume 14h video volume 16h aux volume 18h pcm out volume table 4. stereo volume register index d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sl2 sl1 sl0 sr2 sr1 sr0 sx2 - sx0 record source 0mic 1 cd input 2 video input 3 aux input 4 line input 5stereo mix 6 mono mix 7 phone input table 5. input mux selection d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute gl3 gl2 gl1 gl0 gr3 gr2 gr1 gr0
20 ds319pp3 CS4299 crystalclear? soundfusion? audio codec 97 general purpose (index 20h) mix mono output path. when clear, the mono mix out (a mix of the 5 analog stereo sources plus pcm_out) is selected for mono_out. when set, the mic path is sent to mono out. ms microphone select. determines which of the two mic inputs are passed to the mixer. when set, mic2 input is selected; when clear mic1 is selected. lpbk loopback. if set, enables adc/dac loopback mode. 3d 3d enable. if set, enables the crystalclear 3d stereo enhancement. default 0000h. 3d control (index 22h) s[3:0] spacial enhancement depth. spacial enhancement is enabled by the 3d bit in the general purpose (index 20h) register. 0000 - no spacial enhancement. 1111 - full special enhancement. default 0000h, no spacial enhancement added. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 3d mix ms lpbk d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 s3 s2 s1 s0
ds319pp3 21 CS4299 crystalclear? soundfusion? audio codec 97 powerdown control/status (index 26h) eapd external amplifier power down. the eapd pin follows this bit. generally used to power-down ex- ternal amplifiers. pr6 when set, the alternate line-out buffer is powered down. pr5 when set, the internal master clock is disabled. the only way to recover from setting this bit is through a cold ac 97 reset (driving the reset# signal active). pr4 when set, the ac link is powered down. the ac link can be restarted through a warm ac 97 reset using the sync signal, or a cold ac 97 reset using the reset# signal (the primary codec only). pr3 when set, the analog mixer and voltage reference are powered down. when clearing this bit, the anl, adc, and dac bits should be checked before writing any mixer registers. pr2 when set, the analog mixer is powered down (the voltage reference is still active). when clearing this bit, the anl bit should be checked before writing any mixer registers. pr1 when set, the dacs are powered down. when clearing this bit, the dac bit should be checked be- fore sending any data to the dacs. pr0 when set, the adcs and the adc input muxes are powered down. when clearing this bit, no valid data will be sent down the ac link until the adc bit goes high. ref voltage reference ready status. when set, indicates the voltage reference is at a nominal level. anl analog ready status. when set, the analog output mixer, input multiplexer, and volume controls are ready. when clear, no volume control registers should be written. dac dac ready status. when set, the dacs are ready to receive data across the ac link. when clear, the dacs will not accept any valid data. adc adc ready status. when set, the adcs are ready to send data across the ac link. when clear, no data will be sent to the controller. default 0000h, all blocks are powered on. the lower four bits will eventually change as the codec finishes an initialization and calibration sequence. the pr[6:0] and the eapd bits are power-down control for different sections of the codec as well as external amplifiers. the ref, anl, dac, and adc bits are status bits which, when set, indicate that a particular section of the codec is ready. after the controller receives the codec ready bit in slot 0, these status bits must be checked before writing to any mixer registers. extended audio id (index 28h) id[1:0] codec configuration id. primary is 00; secondary is 01,10,or 11. this is a reflection of the id[1:0]# configuration pins. the state of the id# pins are determined at power-up and are the inverse of the id bits in this register. amap ac link mapping. when set, this device supports the ac 97, revision 2.1, ac-link slot to audio dac mapping. this is a reflection of the amen bit in the slot map (index 5eh) register. vra variable rate audio. this bit is set by default for the CS4299 indicating variable sample rates are supported. read-only data x201h. where x is determined by the state of id[1:0] input pins. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 eapd pr6 pr5 pr4 pr3 pr2 pr1 pr0 ref anl dac adc d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 id1 id0 amap vra
22 ds319pp3 CS4299 crystalclear? soundfusion? audio codec 97 extended audio status / control (index 2ah) vre variable rate audio enable. when set, the vre bit enables access to the sample rate registers pcm front dac rate (index 2ch) register and pcm lr adc rate (index 32h) register. when cleared, all accesses to the sample rate registers are ignored and will force the default value of the two pcm registers to bb80h, corresponding to 48 khz sample rate. vre is listed as the vra bit in the extended audio status control register in the ac 97 specification. default 0000h. pcm front dac rate (index 2ch) sr[15:0] front dac sample rate. can only be written when the vre bit of the extended audio status / con- trol (index 2ah) register is set. if the vre bit is clear, all writes are ignored and the register reads back bb80h; corresponding to a 48 khz sample rate. if the vre bit is set, the seven standard sam- ple rates are available. if a value not listed in table 6 is written, the closest sample rate is chosen. writing a non-supported value will reflect the closest supported rate, not the written value. default bb80h, indicating 48 khz sample rate.. pcm lr adc rate (index 32h) sr[15:0] left / right adc sample rate. if the vre bit is clear, all writes are ignored and the register reads back bb80h; corresponding to a 48 khz sample rate. if the vre bit is set, the seven standard sam- ple rates are available. if a value not listed in table 6 is written, the closest sample rate is chosen. writing a non-supported value will reflect the closest supported rate, not the written value. default bb80h, indicating 48 khz sample rate. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 vre d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 sample rate (hz) sr[15:0] sr[15:12] decode 8,000 1f40 0 or 1 11,025 2b11 2 16,000 3e80 3 22,050 5622 4 or 5 32,000 7d00 6 or 7 44,100 ac44 8,9,ah 48,000 bb80 bh,ch,dh,eh,fh table 6. standard sample rates d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0
ds319pp3 23 CS4299 crystalclear? soundfusion? audio codec 97 slot map (index 5eh) ddm dac direct mode. this bit controls the source to the line and alternate line output drivers. when set, the left and right dac directly drive the line and alternate line outputs by bypassing the audio mixer. when clear, the audio mixer is the source for the line and alternate line outputs. amen alternate slot map enable. this bit determines if the CS4299 responds to the codec id to slot map- ping. if clear, the slot mapping will be determined by the state of the sm[1:0] bits. if set, the slot map- ping will be determined by the state of the id[1:0] bits of the extended audio id (index 28h) register . sm[1:0] slot map. determine which ac-link slots the adc and dac data are transferred through. see table 7 and table 8. default 0080h amen, sm[1:0] and the id[1:0] bits of the extended audio id (index 28h) register define the slots assigned for the capture adcs and the playback dacs. the capture slot assignments are listed in table 7 and the playback slot assignments are in table 8. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ddm amen sm1 sm0 slot frame definition id1 id0 amap* sm1 sm0 adc mapping 3 left channel pcm capture data xx 0 0 0 left 0x 1 x x left 4 right channel pcm capture data xx 0 0 0 right 0x 1 0 0 right 5 right channel pcm capture data x x 0 0 1 left 6 microphone xx 0 0 1 right 11 1 x x left 7 left channel pcm capture data xx 0 1 0 left 10 1 x x left 8 right channel pcm capture data xx 0 1 0 right 10 1 x x right 9 left channel pcm capture data xx 0 1 1 left 11 1 x x right 10 right channel pcm capture data x x 0 1 1 right 11 unused 12 * amap is controlled by amen located in slot map (index 5eh) register. table 7. capture slot assignments
24 ds319pp3 CS4299 crystalclear? soundfusion? audio codec 97 s/pdif control (index 68h) please contact crystal semiconductor for additional information on the s/pdif control register. default 0000h. vendor id1 (index 7ch) f[7:0] first character of vendor id. 43h - ascii c character. s[7:0] second character of vendor id. 52h - ascii r character. read-only data 4352h. slot frame definition id1 id0 amap* sm1 sm0 dac mapping 3 left channel pcm playback data xx 0 0 0 left 0x 1 x x left 4 right channel pcm playback data xx 0 0 0 right 0x 1 x x right 5 modem line 1 pcm output data x x 0 0 1 left 6 pcm center channel output data xx 0 0 1 right 11 1 x x left 7 pcm left surround channel output data xx 0 1 0 left 10 1 x x left 8 pcm right surround channel output data xx 0 1 0 right 10 1 x x right 9 pcm low frequency effects output data xx 0 1 1 left 11 1 x x right 10 modem line 1 pcm output data x x 0 1 1 right 11 unused 12 * amap is controlled by amen located in slot map (index 5eh) register. table 8. playback slot assignment d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 spen v 0 0 l cc6 cc5 cc4 cc3 cc2 cc1 cc0 pre copy #audio d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 f7 f6 f5 f4 f3 f2 f1 f0 s7 s6 s5 s4 s3 s2 s1 s0
ds319pp3 25 CS4299 crystalclear? soundfusion? audio codec 97 vendor id2 (index 7eh) t[7:0] third character of vendor id. 59h - ascii y character. pid[2:0] part id. 011 - CS4299. rid[2:0] revision. 001 - revision a. read-only data 5931h. the two vendor id registers provide a means to determine the manufacturer of the ac 97 codec. the first three bytes of the id registers contain the ascii code for the first 3 letters of crystal (cry). the final byte of the vendor id2 register is divided into a part id field and a revision field. table 9 lists the part ids defined to date. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 t7 t6 t5 t4 t3 t2 t1 t0 pid2 pid1 pid0 rid2 rid1 rid0 cid2-cid0 part name 000 cs4297 001 cs4297a 010 cs4294/cs4298 011 CS4299 table 9. reg. 7eh defined part ids
26 ds319pp3 CS4299 crystalclear? soundfusion? audio codec 97 5.0 power management the powerdown control/status register (index 26h) controls the power management functions. sev- en of these bits (bits 14:8) have defined functions. in effect, all portions of the codec can be shut down individually and powered back up by a single cold or warm reset sequence. table 10 shows the mapping of the power control bits to the functions they manage: when, for example, pr0 is set, the main adcs and the input mux are shut down and the adc bit (bit 0 in the powerdown control/status (index 26h) register) is cleared indicating the adcs are no longer in a ready state. the same is true for the dacs, the analog mixers, and the reference voltage (vrefout). when the pr2 or pr3 bit of the mixer is cleared, the mixer section will begin a power-on process, and the corresponding powerdown status bit will be set when the hardware is ready. bit pr4, which shuts down the ac-link, causes the primary codec to turn off the bit_clk and drive sdata_in low. it also ignores sync and sdata_out in their normal capacities. to restore op- eration to the part from this state, either a cold or a warm reset is required (see cold ac 97 reset and warm ac 97 reset sections). a cold reset will restore all mixer registers to their power-on de- fault values. a warm reset will not alter the values of any mixer register (with the exception of clear- ing the pr4 bit of powerdown control/status (index 26h) register. the pr5 bit is a global codec powerdown that forces all internal clocks to shut down. a cold reset is the only way to restore operation to the CS4299 after a global powerdown. the CS4299 does not automatically mute any input or output when the powerdown bits are set. the software driver controlling the ac 97 device must manage muting the input and output analog sig- nals before putting the part into any power management state. 6.0 analog hardware description the analog hardware consist of four line-level stereo inputs, two selectable mono microphone inputs, two mono inputs, a mono output, and dual, independent stereo line outputs. this section describes the analog hardware needed to interface with these pins. 6.1 line-level inputs the analog inputs consist of four stereo analog inputs and four mono inputs. as shown in figure 3 on page 11, the input to the adcs comes from the input mux which selects one of the following: phone (mono), aux, video, cd, mic1 or mic2 (mono), line, stereo output mix, or the mono out- pr bit function pr0 main adcs and input mux powerdown pr1 main dacs powerdown pr2 analog mixer powerdown (vref on) pr3 analog mixer powerdown (vref off) pr4 ac-link powerdown (bit_clk off)* pr5 internal clock disable pr6 alternate line out buffer powerdown * applies only to primary codec table 10. powerdown pr bit functions
ds319pp3 27 CS4299 crystalclear? soundfusion? audio codec 97 put mix (mono). unused analog inputs should be connected together and then connected through a capacitor to analog ground or tied to the vrefout line directly. the analog input mixer is designed to accommodate five stereo inputs and one mono input. these inputs are: a stereo line-level input (line), a mono micro- phone input (mic), a stereo cd-rom input (cd), a stereo auxiliary line-level input (aux), and the pcm output from the dacs. each of the stereo inputs has separate volume controls for each channel and one mute control for each left/right pair. the mono micro- phone input has one mute and one volume control. all analog inputs to the CS4299, including cd_gnd, should be capacitively coupled to the input pins. since many analog levels can be as large as 2 v rms , the circuit shown in figure 4 can be used to attenuate the analog input by 6 db (to 1v rms) which is the maximum voltage allowed for all the stereo line-level inputs. the cd line-level inputs have an extra pin, cd_gnd, which provides a pseudo-differential input for both cd_l and cd_r. this pin takes the common-mode noise out of the cd inputs when connected to the ground coming from the cd analog source. connecting the cd pins as shown in figure 5 provides extra attenuation of common mode noise coming from the cdrom drive, thereby producing a higher quality signal. one percent resistors are recommended since the better the resistors match, the better the common-mode attenuation of unwanted signals. if cd is not used, the inputs should be connected through ac capacitors to analog ground or connected to vrefout. 6.2 microphone level inputs the microphone level inputs, mic1 and mic2, include a selectable -34.5 db to +12 db gain stage for interfacing to an external microphone. an additional 20 db gain block is also available. figure 6 illustrates a single-ended microphone input buffer circuit that will support lower gain dynamic mi- crophones, and phantom-powered microphones that use the right channel (ring) of the jack for pow- er. 6.3 mono inputs the mono input, pc_beep, is useful for mixing the output of the beeper (timer chip), provided in all pcs, with the rest of the audio signals. when the part is held in reset, the CS4299 passes the pc_beep input directly to the line output. this allows the system sounds or beep to be available before the ac 97 interface has been activated. this feature is controlled by the beep_en pin. by default, (the beep_en pin unconnected or pulled high) the CS4299 enables the pc_beep to line out path while the reset pin is active.the attenuation control allows 16 levels in -3 db steps. in addition, a mute control is provided. the attenuator is a single channel block with the resulting signal sent to the output mixer where it is mixed with the left and right outputs. figure 7 illustrates a typical 6.8 k w 6.8 k w 1.0 m f 1.0 m f r l 6.8 k w 6.8 k w figure 4. line inputs 6.8 k w 6.8 k w 1.0 m f 1.0 m f cd_l cd_r 6.8 k w 6.8 k w 3.4 k w cd_gnd 2.0 m f 3.4 k w (all resistors 1%) figure 5. differential cdrom in
28 ds319pp3 CS4299 crystalclear? soundfusion? audio codec 97 input circuit for the pc_beep input. if pc_beep is driven from a cmos gate, the 4.7 k w should be tied to analog ground instead of va+. although this input is described for a low-quality beeper, the input is of the same high-quality as all other analog inputs and may be used for other purposes. the mono input, phone, can be used to inter- face to the output of a modem analog front end (afe) chip so that modem dialing signals and protocol negotiations may be monitored through the audio system. like all other analog inputs, this pin must be ac coupled and the in- put signal must be limited to 1 v rms . 6.4 line level outputs the analog output section provides a stereo line-level output and an alternate stereo line-level output. line_out_l, line_out_r, alt_line_out_l, and alt_line_out_r outputs should be capacitively coupled to external circuitry. the mono output, mono_out, can be either a sum of the left and right output channels, attenuated by 6 db to prevent clipping at full scale, or the selected mic_in signal. the mono out channel can drive the pc internal mono speaker using an appropriate buffer circuit the mute control is indepen- dent of the line outputs allowing the mono channel to mute the speaker without muting the line out- puts. each of the 5 analog outputs, if used in the design, require 680 pf to 1000 pf npo dielectric capac- itors between the corresponding pin and analog ground. each analog output is dc biased up to the agnd 4 8 +5 va 100 k w 1 2 5 3 4 2.7 k w cgnd 220 pf 220 pf 68 k w agnd 0.068 f x7r agnd + - agnd 4 1 8 +5 va u1a mc33078d 3 2 47 k w 10 f agnd 2 1 + 47 k w agnd +5 va 47 k w + - 6.8 k w 10 f agnd 2 1 + 6 5 220 pf 47 k w u1b mc33078d 1 f x7r 7 mic1 figure 6. pc 99 microphone pre-amplifier 2.7 nf 47 k w 4.7 k w 0.1 m f pc_beep 1 +5va (low noise) or agnd - if cmos source figure 7. mono input
ds319pp3 29 CS4299 crystalclear? soundfusion? audio codec 97 vrefout voltage signal reference which is nominally 2.2 v. this requires that the output either be ac coupled to external circuitry (ac load must be greater than 10 k w ) or dc coupled to a buffer op-amp biased at the vrefout voltage (see figure 8 for the recommended headphone op-amp circuit). 6.5 miscellaneous analog signals the aflt1 and aflt2 pins must have a 1000 pf npo capacitor to analog ground. these capaci- tors, along with an internal resistor, provide a single-pole low-pass filter at the inputs to the adcs. by placing these filters at the input to the adcs, low-pass filters at each analog input pin are not nec- essary. the refflt pin lowers the noise of the internal voltage reference. a 1 m f (must not be greater than 1 m f) and 0.1 m f capacitor to analog ground should be connected with a short, wide trace to this pin (see figure 11 in the grounding and layout section for an example). no other connection should be made, as any coupling onto this pin will degrade the analog performance of the codec. likewise, dig- ital signals should be kept away from refflt for similar reasons.the vrefout pin is typically 2.2 v and provides a common mode signal for single-supply external circuits. vrefout only supports light dc loads and should be buffered if ac loading is needed. for typical use, a 0.1 m f in parallel with a 1 m f capacitor should be connected to vrefout. 6.6 consumer iec-958 digital interface (s/pdif) the CS4299 supports the industry standard iec-958 consumer digital interface. sometimes this in- terface is referred to as s/pdif, which refers to an older version of this standard. this output provides an interface, external to the pc, for storing digital audio data or playing digital audio data to digital speakers. figure 9 illustrates the circuit necessary for implementation of the iec-958 optical or con- sumer interface. agnd alt_line_out_r 27 k w 1000 pf npo 1000 pf npo 1 2 3 4 agnd 0.1 f y5v 220 f + 5 - 39 k w 1 2 3 4 + 3 - 22 pf npo 22 pf npo 6 2 7 1 tda1308 tda1308 alt_line_out_l vrefout + elec 1/4 watt 10 w hp_out_r 220 f + elec 1/4 watt 10 w hp_out_l 47 k w 1 3 4 agnd 2 1 f figure 8. headphones driver
30 ds319pp3 CS4299 crystalclear? soundfusion? audio codec 97 6.7 power supplies the power supplies providing analog power should be as clean as possible to minimize cou- pling into the analog section which could degrade analog performance. the pins avdd1 and avdd2 supply power to all the analog circuitry on the CS4299. this 5 volt analog supply should be gen- erated from a voltage regulator (7805 type) con- nected to a +12 volt supply. this helps isolate the analog circuitry from noise typically found on +5 v digital supplies which power many digital circuits in a pc environment. a typical voltage regulator circuit for analog power using an mc78m05cdt is shown in figure 10. the digital power pins dvdd1 and dvdd2 should be connected to the same digital supply as the controllers ac-link interface. since the digital interface on the codec may operate at either 3.3 v or 5 v, proper connec- tion of these pins will depend on the digital power supply of the controller. 7.0 grounding and layout figure 11 is the suggested layout for the codec. the decoupling capacitors should be located physi- cally as close to the pins as possible. also note the routing of the refflt decoupling capacitors and the isolation of that ground strip. it is strongly recommended that the device be located on a locally separate analog ground plane. this analog ground plane keeps noise from digital ground return currents from modulating the codecs ground potential and degrading performance. the digital ground pins should be connected to the dig- ital ground plane and kept separate from the analog ground connections of the codec and any other external analog circuitry. dgnd dgnd dgnd dgnd 1 2 1 2 374 90.9 1 5 4 8 1 2 j-rca-r4-pcb gnd vcc 1 2 4 5 +5 v pci 0.1 m f sn75179d dgnd dgnd dgnd +5v_pci spdifo totx-173 1 2 3 4 5 6 8.2k .1 m f spdifo figure 9. iec-958 interface examples figure 10. voltage regulator +12vd agnd dgnd +5va 0.1 f y5v 10f elec + 10f elec + mc78m05cdt out 3 gnd 2 in 1 0.1f y5v
ds319pp3 31 CS4299 crystalclear? soundfusion? audio codec 97 the common connection point between the two ground planes (required to maintain a common ground voltage potential) should be located near the codec just under the digital ground connec- tions (vias). the ac-link digital interface con- nection traces should be routed such that the digital ground plane lies underneath these sig- nals (on the internal ground layer) from the ac 97 controller continuously to the codec. analog ground to digital ground pin 1 0.1 f 1000 pf npo 1 f to analog ground to +5va to +5vd 0.1 f y5v to +5vd 0.1 f y5v y5v 0.1 f y5v to +5va avdd2 avss2 aflt2 aflt1 refflt avss1 avdd1 dvss1 dvss2 dvdd2 dvdd1 vrefout to via to analog ground figure 11. suggested layout for the CS4299
32 ds319pp3 CS4299 crystalclear? soundfusion? audio codec 97 8.0 pin descriptions digital i/o pins reset# - ac 97 chip reset, input this active low signal is the asynchronous cold reset input to the CS4299. the CS4299 must be reset before it can enter normal operating mode. sync - ac-link serial port sync pulse, input this signal is the serial port timing signal for the ac-link. its period is the reciprocal of the maximum sample rate, 48 khz, and is generated by the ac 97 controller synchronous to bit_clk. sync is also an asynchronous input when the codec is in a warm reset state. a series terminating resistor of 47 w should be connected on this signal close to the controller. c d _ au x _ v i d e o_ cd_ m i c phon au x _ v i d e o_ cd_gn m i c l i ne _ i n _ l i ne _ i n _ l l l r 2 e r r d 1 l r bpcfg l ine _ o ut_l flti aflt1 refflt l i n e _ o ut_r flto flt3d aflt2 vrefout avss1 avdd1 n c a v d d 2 mo n o _ o u t 6 2 4 8 10 1 3 5 7 9 11 12 13 14 15 16 17 18 19 20 21 22 23 24 31 35 33 29 27 36 34 32 30 28 26 25 48 47 46 45 44 43 42 41 40 39 38 37 CS4299-xq bit_clk xtl_in dvss1 sdata_in sync dvdd1 xtl_out sdata_out dvdd2 reset# pc_beep dvss2 alt_line_out_r alt_line_out_l nc eapd id0# s/pdif_out id1# nc av s s2 (48-pin tqfp)
ds319pp3 33 CS4299 crystalclear? soundfusion? audio codec 97 bit_clk - ac-link serial port master clock, input/output this input/output signal controls the master clock timing for the ac-link. when the codec is in primary mode, this signal is a 12.288 mhz output clock signal divided down by two from the xtl_in input clock pin. when the codec is in secondary mode, this signal is an input which controls the ac-link serial interface and generates all internal clocking. a series terminating resistor of 47 w should be connected on this signal close to the primary codec driving bit_clk. sdata_out - ac-link serial data input stream to ac 97, input this input signal transmits the control information and digital audio output streams to be sent to the dacs. the data is clocked into the codec on the falling edge of bit_clk. a series terminating resistor of 47 w should be connected on this signal close to the controller. sdata_in - ac-link serial data output stream from ac 97, output this output signal transmits the status information and digital audio input streams from the adcs. the data is clocked out of the codec on the rising edge of bit_clk. a series terminating resistor of 47 w should be connected on this signal as close to the codec as possible. xtl_in - crystal input when in primary mode, this pin requires either a crystal, with the other pin attached to xtl_out, or an external cmos clock. the crystal frequency must be 24.576 mhz and designed for fundamental mode, parallel resonance operation. when configured as a secondary codec, all timing is derived from the bit_clk input signal; this pin should be left floating. xtl_out - crystal output used for a crystal placed between this pin and xlt_in. if an external clock is used on xtl_in, this pin must be left floating with no traces or components connected to it. when configured as a secondary codec, this pin should be left floating. id1#, id0# - codec id, inputs these pins select the codec id and mode of operation for the codec. their value is sampled and latched on the rising edge of reset#. these inputs use the digital supply bus for their value and contain internal pull-up resistors to the digital supply bus rail. the pins utilize inverted logic, so a value of 1:1 sets the codec to primary mode while any other combination sets the codec to secondary mode. in primary mode, the codec is always clocked from an external crystal or an external oscillator connected to the xtl_in and/or xtl_out pins with bit_clk as an output. when either or both ids are tied to analog ground, the codec is in secondary mode and bit_clk is always an input. s/pdif - iec-958 consumer digital output, output this output provides a digital interface to devices external to the pc. with the appropriate buffer, the output can drive the iec-958 consumer interface or directly drive an optical transmitter.
34 ds319pp3 CS4299 crystalclear? soundfusion? audio codec 97 bpcfg - pc beep enable, input this input controls the pc_beep input when the device is held in reset. when unconnected or pulled high through an external pull-up resistor, the pc_beep input is enabled. grounding this input disables the pc_beep when reset is active. the pin is pulled high through an internal 100 k w resistor. eapd - external amplifier power down, output this signal is designated as a power down control for audio amplifiers external to the codec. the output is determined by the eapd bit and is low by default. analog i/o pins pc_beep - analog mono source, input this signal is generally used as an internal pc beep connection to the audio subsystem. this source is not input to the stereo-to-mono mixer. the maximum allowable input is 1 v rms (sinusoidal). this input is internally biased at the vrefout voltage reference and requires ac coupling to external circuitry. if this input is not used, it should be connected to the vrefout pin or ac coupled to analog ground. phone - analog mono source, input this signal is generally used as a voice modem connection to the audio subsystem. this source is not input to the stereo-to-mono mixer. the maximum allowable input is 1 v rms (sinusoidal). this input is internally biased at the vrefout voltage reference and requires ac coupling to external circuitry. if this input is not used, it should be connected to the vrefout pin or ac coupled to analog ground. mic1 - analog mono source, input this analog input is a monophonic source to the analog output mixer. it is generally used as a desktop microphone connection to the audio subsystem. this input is mux-selectable to the input mixer with the mic2 input source. the maximum allowable input is 1 v rms (sinusoidal). this input is internally biased at the vrefout voltage reference and requires ac coupling to external circuitry. if this input is not used, it should be ac coupled to analog ground. mic2 - analog mono source, input this analog input is a monophonic source to the analog output mixer. it is generally used as an alternate microphone connection to the audio subsystem. this input is mux-selectable to the input mixer with the mic1 input source. the maximum allowable input is 1 v rms (sinusoidal). this input is internally biased at the vrefout voltage reference and requires ac coupling to external circuitry. if this input is not used, it should be ac coupled to analog ground. line_in_l and line_in_r- analog line source, inputs these inputs form a stereo input pair to the codec. the maximum allowable input is 1 v rms (sinusoidal). these inputs are internally biased at the vrefout voltage reference. ac coupling to external circuitry is required. if these inputs are not used, they should both be connected to the vrefout pin or both ac coupled, with separate ac coupling caps, to analog ground.
ds319pp3 35 CS4299 crystalclear? soundfusion? audio codec 97 cd_l and cd_r - analog cd source, inputs these inputs form a stereo input pair. generally used for the redbook cd audio connection to the audio subsystem. the maximum allowable input is 1 v rms (sinusoidal). these inputs are internally biased at the vrefout voltage reference. ac coupling to external circuitry is required. if these inputs are not used, they should both be connected to the vrefout pin or both ac coupled, with separate ac coupling caps, to analog ground. cd_gnd - analog cd common source, input this analog input is used to remove common mode noise from redbook cd audio signals. the impedance on the input signal path should be one half the impedance on the cd_l and cd_r input paths. this pin requires ac coupling to external circuitry. if this input is not used, it should be connected to the vrefout pin or ac coupled to analog ground. video_l and video_r - analog video audio source, inputs these inputs form a stereo input pair. it is generally used for the audio signal output of a video device. the maximum allowable input is 1 v rms (sinusoidal). these inputs are internally biased at the vrefout voltage reference. ac coupling to external circuitry is required. if these inputs are not used, they should both be connected to the vrefout pin or both ac coupled, with separate ac coupling caps, to analog ground. aux_l and aux_r - analog auxiliary source, inputs these inputs form a stereo input pair. the maximum allowable input is 1 v rms (sinusoidal). these inputs are internally biased at the vrefout voltage reference. ac coupling to external circuitry is required. if these inputs are not used, they should both be connected to the vrefout pin or both ac coupled, with separate ac coupling caps, to analog ground. line_out_l and line_out_r - analog line level outputs these signals are analog outputs from the stereo output mixer. the full scale output voltage for output is nominally 1 v rms and is internally biased at the vrefout voltage reference. it is required to either ac couple these pins to external circuitry or dc couple them to a buffer op-amp biased at the vrefout voltage. these pins need a 680 pf to 1000 pf npo capacitor attached to analog ground. alt_line_out_l and alt_line_out_r - analog alternate line level outputs these signals are analog outputs from the stereo output mixer. the full scale output voltage for each output is nominally 1 v rms and is internally biased at the vrefout voltage reference. it is required to either ac couple these pins to external circuitry or dc couple them to a buffer op-amp biased at the vrefout voltage. these pins need a 680 pf to 1000 pf npo capacitor attached to analog ground.
36 ds319pp3 CS4299 crystalclear? soundfusion? audio codec 97 mono_out, analog mono line level output this signal is an analog output from the mono output mixer or mic1/2. when the mono output mixer is selected, the left and right channels are mixed from the output of the stereo input mixer. when the mic mode is selected, mic1 or mic2 is routed to the mono_out. the full scale output is nominally 1 v rms and is internally biased at the vrefout voltage reference. ac coupling to external circuitry is required. this pin needs a 680 pf to 1000 pf npo capacitor attached to analog ground. filter and reference pins refflt - internal reference voltage, input this is the voltage reference used internal to the part. a 0.1 m f and a 1 m f (must not be larger than 1 m f) capacitor with short, wide traces must be connected to this pin. no other connections should be made to this pin. vrefout - voltage reference, output all analog inputs and outputs are centered around vrefout which is nominally 2.2 volts. this pin may be used to level shift external circuitry, however any external loading should be buffered. aflt1 - left channel antialiasing filter input this pin needs a 1000 pf npo capacitor attached to analog ground. aflt2 - right channel antialiasing filter input this pin needs a 1000 pf npo capacitor attached to analog ground. flti - flto - 3d filter a 1000 pf capacitor must be attached between flti and flto if the 3d function is used. flt3d - 3d filter a 0.01 m f capacitor must be attached from this pin to agnd if the 3d function is used. power supplies dvdd1, dvdd2 - digital supply voltage digital supply voltage for the ac-link section of the codec. these pins can be tied to +5 v digital or to +3.3 v digital. the codec and controllers ac-link should share a common digital supply dvss1, dvss2 - digital ground digital ground connection for the ac-link section of the codec. these pins should be isolated from analog ground currents.
ds319pp3 37 CS4299 crystalclear? soundfusion? audio codec 97 avdd1, avdd2 - analog supply voltage analog supply voltage for the analog and mixed signal sections of the codec. these pins must be tied to +5 volt power supply. it is strongly recommended that +5 volts be generated from a voltage regulator to ensure proper supply currents and noise immunity from the rest of the system. avss1, avss2 - analog ground ground connection for the analog, mixed signal, and substrate sections of the codec. these pins should be isolated from digital ground currents.
38 ds319pp3 CS4299 crystalclear? soundfusion? audio codec 97 9.0 parameter and term definitions ac 97 specification refers to the audio codec 97 component specification ver 2.1 published by intel ? corporation [1]. ac 97 controller or controller refers to the control chip which interfaces to the codecs ac-link. this has been also called dc 97 for digital controller 97 [1]. ac 97 registers or codec registers refers to the 64-field register map defined in the ac 97 specification. adc refers to a single analog-to-digital converter in the codec. adcs refers to the stereo pair of analog-to-digital converters. dac a single digital-to-analog converter in the codec dacs refers to the stereo pair of digital-to-analog converters. src sample rate converter. converts data derived at one sample rate to a differing sample rate. codec refers to the chip containing the adcs, dacs, and analog mixer. in this data sheet, the codec is the CS4299. fft fast fourier transform. resolution the number of bits in the output words to the dacs, and in the input words to the adcs. differential nonlinearity the worst case deviation from the ideal code width. units in lsb. db fs a db fs is defined as db relative to full-scale. the a indicates an a weighting filter was used.
ds319pp3 39 CS4299 crystalclear? soundfusion? audio codec 97 frequency response (fr) fr is the deviation in signal level verses frequency. the 0 db reference point is 1 khz. the amplitude corner, ac, lists the maximum deviation in amplitude above and below the 1 khz reference point. the listed minimum and maximum frequencies are guaranteed to be within the ac from minimum frequency to maximum frequency inclusive. dynamic range (dr) dr is the ratio of the rms full-scale signal level divided by the rms sum of the noise floor, in the presence of a signal, available at any instant in time (no change in gain settings between measurements). measured over a 20 hz to 20 khz bandwidth with units in db fs a. total harmonic distortion plus noise (thd+n) thd+n is the ratio of the rms sum of all non-fundamental frequency components, divided by the rms full-scale signal level. it is tested using a -3 db fs input signal and is measured over a 20 hz to 20 khz bandwidth with units in db fs. signal to noise ratio (snr) snr, similar to dr, is the ratio of an arbitrary sinusoidal input signal to the rms sum of the noise floor, in the presence of a signal. it is measured over a 20 hz to 20 khz bandwidth with units in db. s/pdif sony/phillips digital interface. this interface was established as a means of digitally interconnecting consumer audio equipment. the documentation for s/pdif has been superseded by the iec-958 consumer digital interface document. interchannel isolation the amount of 1 khz signal present on the output of the grounded ac-coupled line input channel with 1 khz, 0 db, signal present on the other line input channel. units in db. interchannel gain mismatch for the adcs, the difference in input voltage to get an equal code on both channels. for the dacs, the difference in output voltages for each channel when both channels are fed the same code. units in db. paths a-d: analog in, through the adc, onto the serial link. d-a: serial interface inputs through the dac to the analog output. a-a: analog in to analog out (analog mixer).
40 ds319pp3 CS4299 crystalclear? soundfusion? audio codec 97 10.0 references 1) intel, audio codec 97 component specification , revision 2.1, may 22,1998. http://developer.intel.com/pc-supp /platform/ac97 /
ds319pp3 41 CS4299 crystalclear? soundfusion? audio codec 97 11.0 package dimensions inches millimeters dim min max min max a ---- 0.063 ---- 1.600 a1 0.002 0.006 0.050 0.150 b 0.007 0.011 0.170 0.270 d 0.343 0.366 8.700 9.300 d1 0.272 0.280 6.900 7.100 e 0.343 0.366 8.700 9.300 e1 0.272 0.280 6.900 7.100 e* 0.016 0.024 0.400 0.600 l 0.018 0.030 0.450 0.750 0.000 7.000 0.000 7.000 * nominal pin pitch is 0.50 mm controlling dimension is mm. jedec designation: ms026 48l tqfp package drawing e1 e d1 d 1 e l b a1 a

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